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tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 1 post office box 1443 ? houston, texas 772511443 organizatio n...262144 by 8 bits single 5-v power supply operationally compatible with existing megabit eproms industry standard 32-pin dual-in-line package and 32-lead plastic leaded chip carrier all inputs / outputs fully ttl compatible 10% v cc tolerance max access / min cycle time v cc 10% '27c/ pc020-10 100 ns '27c/ pc020-12 120 ns '27c/ pc020-15 150 ns '27c/ pc020-20 200 ns '27c/ pc020-25 250 ns 8-bit output for use in microprocessor-based systems very high-speed snap! pulse programming power saving cmos technology 3-state output buffers 400 mv minimum dc noise immunity with standard ttl loads latchup immunity of 250 ma on all input and output pins no pullup resistors required low power dissipation (v cc = 5.5 v) activ e... 165 mw worst case standb y... 0.55 mw worst case (cmos-input levels) temperature range options description the tms27c020 series are 262 144 by 8-bit (2 097 152-bit), ultraviolet (uv) light erasable, electrically programmable read-only memories (eproms). the tms27pc020 series are one-time program- mable (otp) electrically programmable read-only memories (proms). please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 3213231 14 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 430 15 16 17 18 19 20 j package ( top view ) pin nomenclature a0 a17 address inputs dq0 dq7 inputs (programming) / outputs e chip enable g output enable gnd ground pgm program v cc 5-v power supply v pp 13-v power supply 2 2only in program mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v pp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd v cc pgm a17 a14 a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 a14 a13 a8 a9 a11 g a10 e dq7 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 dq3 dq4 dq5 a12 a15 a16 v pgm a17 tms27pc020 fm package ( top view ) dq6 cc v pp gnd copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 2 post office box 1443 ? houston, texas 772511443 description (continued) these devices are fabricated using power-saving cmos technology for high speed and simple interface with mos and bipolar circuits. all inputs ( including program data inputs) can be driven by series 74 ttl circuits without the use of external pullup resistors. each output can drive one series 74 ttl circuit without external resistors. the tms27c020 eprom is offered in a dual-in-line ceramic package (j suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. the tms27c020 is also offered with two choices of temperature ranges of 0 to 70 c (jl suffix) and 40 c to 85 c (je suffix). see table 1. the tms27pc020 is offered in a 32-lead plastic leaded chip carrier using 1,25 mm (50 mil) lead spacing ( fm suffix). the tms27pc020 is offered with two choices of temperature ranges of 0 c to 70 c (fml suffix) and 40 c to 85 c (fme suffix). see table 1. table 1. temperature range suffixes function suffix for operating temperature ranges 0 c to 70 c 40 c to 85 c tms27c040-xxx jl je TMS27PC040-xxx fml fme these eproms operate from a single 5-v supply ( in the read mode), they are ideal for use in microprocessor-based systems. one other (13 v) supply is needed for programming. all programming signals are ttl level. for programming outside the system, existing eprom programmers can be used. operation the seven modes of operation for the tms27c020 and tms27pc020 are listed in t able 2. the read mode requires a single 5-v supply. all inputs are ttl level except for v pp during programming (13 v), and v h (12 v) on a9 for the signature mode. table 2. operation modes mode 2 function read output disable standby programming verify program inhibit signature mode e v il v il v ih v il v il v ih v il g v il v ih x v ih v il x v il pgm x x x v il v ih x x v pp x v cc v cc v pp v pp v pp v cc v cc v cc v cc v cc v cc v cc v cc v cc a9 x x x x x x v h 3 v h 3 a0 x x x x x x v il v ih code dq0 dq7 data out hi-z hi-z data in data out hi-z mfg device 97 32 2 x can be v il or v ih 3 v h = 12 v 0.5 v
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 3 post office box 1443 ? houston, texas 772511443 read/ output disable when the outputs of two or more tms27c020s or tms27pc020s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. to read the output of a single device, a low level signal is applied to the e and g pins. all other devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins. latchup immunity latchup immunity on the tms27c020 and tms72pc020 is a minimum of 250 ma on all inputs and outputs. this feature provides latchup immunity beyond any potential transients at the p.c. board level when the eprom is interfaced to industry standard ttl or mos logic devices. the input / output layout approach controls latchup without compromising performance or packing density. power down active i cc supply current can be reduced from 30 ma to 500 m a by applying a high ttl input on e and to 100 m a by applying a high cmos input on e . in this mode all outputs are in the high-impedance state. erasure before programming, the tms27c020 is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 ?). the recommended minimum exposure dose (uv intensity exposure time) is 15-w ? s/cm 2 . a typical 12-mw / cm 2 , filterless uv lamp erases the device in 21 minutes. the lamp should be located about 2.5 cm above the chip during erasure. after erasure, all bits are in the high state. it should be noted that normal ambient light contains the correct wavelength for erasure. therefore, when using the tms27c020, the window should be covered with an opaque label. after erasure (all bits in logic high state), logic lows are programmed into the desired locations. a programmed low can be erased only by ultraviolet light. snap! pulse programming the tms27c020 and tms27pc020 are programmed using the ti snap! pulse programming algorithm, illustrated by the flowchart in figure 1, which programs in a nominal time of twenty-six seconds. actual programming time varies as a function of the programmer used. the snap! pulse programming algorithm uses an initial pulse of 100 microseconds ( m s) followed by a byte verification to determine when the addressed byte has been successfully programmed. up to ten 100- m s pulses per byte are provided before a failure is recognized. the programming mode is achieved when v pp equals 13 v, v cc = 6.5 v, e = v il , g = v ih . data is presented in parallel (eight bits) on pins dq0 through dq7. once addresses and data are stable, pgm is pulsed low. more than one device can be programmed when the devices are connected in parallel. locations can be programmed in any order. when the snap! pulse programming routine is complete, all bits are verified with v cc = v pp = 5 v 10%. program inhibit programming can be inhibited by maintaining a high level input on the e or pgm pins. program verify programmed bits can be verified with v pp equals 13 v when g = v il , e = v il , and pgm = v ih . signature mode the signature mode provides access to a binary code identifying the manufacturer and type. this mode is activated when a9 (pin 26) is forced to 12 v. two identifier bytes are accessed by toggling a0. all other addresses must be held low. the signature code for the tms27c020 is 9732. a0 low selects the manufacturer's code 97 ( hex), and a0 high selects the device code 32 ( hex), as shown in table 3.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 4 post office box 1443 ? houston, texas 772511443 signature mode (continued) table 3. signature mode identifier 2 pins identifier 2 a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex manufacturer code v il 1 0 0 1 0 1 1 1 97 device code v ih 0 0 1 1 0 0 1 0 32 2 e = g = v il , a1 a8 = v il , a9 = v h , a10 a17 = v il , v pp = v cc .
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 5 post office box 1443 ? houston, texas 772511443 start address = first location v cc = 6.5 v 0.25 v, v pp = 13 v 0.25 v last address? address = first location x = 0 v cc = v pp = 5 v 0.5 v compare all bytes to original data device passed increment address increment address verify one byte program one pulse = t w = 100 m s x = 10? x = x + 1 last address? device failed pass no yes yes no fail fail pass no program mode interactive mode final verification yes program one pulse = t w = 100 m s figure 1. snap! pulse programming flowchart
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 6 post office box 1443 ? houston, texas 772511443 logic symbol 2 a0 12 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 e g 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 dq0 13 dq1 dq2 dq3 dq4 dq5 dq6 14 15 17 18 19 20 eprom 262 144 8 a ? a ? a ? a ? a ? a ? a ? a ? dq7 21 0 [pwr down] en & a17 30 17 a 0 262 143 2 this symbol is in accordance with ansi / ieee std 91-1984 and iec publication 617-12. pin numbers are for the j package.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 7 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage range, v cc (see note 1) : 0.6 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v pp : 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range (see note 1), all inputs except a9 : 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . a9 : 0.6 v to 13.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, with respect to v ss (see note 1) : 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range ('27c020-_ _ jl, '27pc020_ _fml) : 0 c to 70 c . . . . . . . . . . . . . . . . . operating free-air temperature range ('27c020-_ _je, '27pc020-_ _fme) : 40 c to 85 c . . . . . . . . . . . . . . . storage temperature range, t stg : 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to gnd. recommended operating conditions min nom max unit v cc su pp ly voltage read mode (see note 2) 4.5 5 5.5 v v cc s u ppl y v oltage snap! pulse programming algorithm 6.25 6.5 6.75 v v pp su pp ly voltage read mode v cc 0.6 v cc v cc + 0.6 v v pp s u ppl y v oltage snap! pulse programming algorithm 12.75 13 13.25 v v ih high level dc in p ut voltage ttl 2 v cc + 0.5 v v ih high - le v el dc inp u t v oltage cmos v cc 0.2 v cc + 0.5 v v il low level dc in p ut voltage ttl 0.5 0.8 v v il lo w- le v el dc inp u t v oltage cmos 0.5 gnd + 0.2 v t a operating free-air temperature '27c020-_ _jl, '27pc020-_ _fml 0 70 c t a operating free-air temperature '27c020-_ _je, '27pc020-_ _fme 40 85 c note 2: v cc must be applied before or at the same time as v pp and removed after or at the same time as v pp . the device must not be inserted into or removed from the board when v pp or v cc is applied. electrical characteristics over full ranges of operating conditions parameter test conditions min max unit v oh high level dc out p ut voltage i oh = 20 m a v cc 0.2 v v oh high - le v el dc o u tp u t v oltage i oh = 2 ma 2.4 v v ol low level dc out p ut voltage i ol = 2.1 ma 0.4 v v ol lo w- le v el dc o u tp u t v oltage i ol = 20 m a 0.1 v i i input current (leakage) v i = 0 v to 5.5 v 1 m a i o output current (leakage) v o = 0 v to v cc 1 m a i pp1 v pp supply current v pp = v cc = 5.5 v 10 m a i pp2 v pp supply current (during program pulse) v pp = 13 v 50 ma i cc1 v cc su pp ly current (standby) ttl-input level v cc = 5.5 v, e = v ih . . . 500 m a i cc1 v cc s u ppl y c u rrent (standb y ) cmos-input level v cc = 5.5 v, e = v cc 0.2 v 100 m a i cc2 v cc supply current (active) v cc = 5.5 v, e = v il t cycle = minimum cycle time, outputs open 2 30 ma 2 minimum cycle time = maximum access time.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 8 post office box 1443 ? houston, texas 772511443 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 mhz 2 parameter test conditions min nom 3 max unit c i input capacitance v i = 0 v, f = 1 mhz 4 8 pf c o output capacitance v o = 0 v, f = 1 mhz 6 10 pf 2 capacitance measurements are made on sample basis only. 3 all typical values are at t a = 25 c and nominal voltages. switching characteristics over full ranges of recommended operating conditions (see notes 3 and 4) test '27c020-10 '27c020-12 '27c020-15 27c020-20 '27c020-25 parameter test conditions ' 27pc020-10 ' 27pc020-12 '27pc020-15 27pc020-20 '27pc020-25 unit conditions min max min max min max min max min max t a(a) access time from address 100 120 150 200 250 ns t a(e) access time from chip en- able 100 120 150 200 250 ns t en(g) output enable time from g cl = 100 pf, 1 series 74 55 55 75 75 100 ns t dis output disable time from g or e , whichever occurs first 2 1 series 74 ttl load, input t r 20 ns, input t f 20 ns 0 50 0 50 0 60 0 60 0 80 ns t v(a) output data valid time after change of ad- dress, e , or g , whichever oc- curs first 0 0 0 0 0 ns value calculated from 0.5-v delta to measured output level. this parameter is sampled and not 100% tested. notes: 3. for all switching characteristics, the input pulse levels are 0.4 v to 2.4 v. timing measurements are made at 2 v for l ogic high and 0.8 v for logic low. (see figure 2). 4. common test conditions apply for t dis except during programming.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 9 post office box 1443 ? houston, texas 772511443 switching characteristics for programming: v cc = 6.5 v and v pp = 13 v (snap! pulse), t a = 25 c (see note 3) parameter min max unit t dis(g) output disable time from g 0 100 ns t en(g) output enable time from g 150 ns note 3: for all switching characteristics the input pulse levels are 0.4 v to 2.4 v. timing measurements are made at 2 v for log ic high and 0.8 v for logic low (see figure 2). timing requirements for programming min typ max unit t w(pgm) pulse duration, program snap! pulse programming algorithm 95 100 105 m s t su(a) setup time, address 2 m s t su(e) setup time, e 2 m s t su(g) setup time, g 2 m s t su(d) setup time, data 2 m s t su(vpp) setup time, v pp 2 m s t su(vcc) setup time, v cc 2 m s t h(a) hold time, address 0 m s t h(d) hold time, data 2 m s
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 10 post office box 1443 ? houston, texas 772511443 parameter measurement information 2.08 v r l = 800 w c l = 100 pf (see note a) output under test 2 v 0.8 v 2 v 0.8 v 2.4 v 0.4 v notes: a. c l includes probe and fixture capacitance. b. the ac testing inputs are driven at 2.4 v for logic high and 0.4 v for logic low. timing measurements are made at 2 v for logic high and 0.8 v for logic low for both inputs and outputs. figure 2. the ac testing output load circuit and waveform a0 a17 e addresses valid t a(a) t a(e) g dq0 dq7 hi-z ten(g) t v(a) t dis output valid v ih v il v ih v il v ih v il v ih v il hi-z figure 3. read-cycle timing
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 11 post office box 1443 ? houston, texas 772511443 parameter measurement information t en(g) 2 a0 a17 dq0 dq7 v pp v cc address stable v ih v il v ih / v oh v il / v ol v pp 3 v cc v cc 3 v cc program verify t su(a) t h(a) t su(d) t su(vpp) t su(vcc) t su(e) t h(d) t su(g) t w(pgm) t dis(g) 2 data-in stable data-out valid address n + 1 e pgm g v ih v il v ih v il v ih v il 2 t dis(g) and t en(g) are characteristics of the device but must be accommodated by the programmer. 3 13-v v pp and 6.5-v v cc for snap! pulse programming. figure 4. program-cycle timing (snap! pulse programming)
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 12 post office box 1443 ? houston, texas 772511443 fm (r-pqcc-j32) plastic j-leaded chip carrier 4040201-4 / b 03/95 0.020 (0,51) 0.015 (0,38) seating plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) nom 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) typ 0.030 (0,76) 0.547 (13,89) 30 1 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 5 4 20 13 14 29 21 0.050 (1,27) 0.004 (0,10) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-016
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 13 post office box 1443 ? houston, texas 772511443 j (r-cdip-t**) ceramic side-braze dual-in-line package 4040084 / b 04/95 b c 0.018 (0,46) min 0.125 (3,18) min 0.022 (0,56) 0.012 (0,30) 0.014 (0,36) 0.008 (0,20) seating plane a wide 24 a pins** dim max min narr 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.235(31,37) 1.235(31,37) 1.265(32,13) 1.265(32,13) min max b c max min 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) narr 32 wide 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) narr 28 wide wide 40 narr 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.032(51,61) 2.032(51,61) 2.068(52,53) 2.068(52,53) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 24 pin shown 1 12 24 13 0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) lens protrusion 0.010 (0,25) max 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0 10 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
tms27c020 262144 by 8-bit uv erasable tms27pc020 262144 by 8-bit programmable read-only memories smls020c november 1990 revised september 1997 14 post office box 1443 ? houston, texas 772511443
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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